Digital-to-analog converter and performing method thereof

ABSTRACT

A digital-to-analog converter and a performing method thereof are disclosed. The digital-to-analog converter includes a random rotation unit, a plurality of conversion units, and a summing unit. The random rotation unit receives a plurality of binary-weighted inputs and generates a plurality of rotated digital outputs according to a random rotation number. The conversion units respectively receive one of the rotated digital outputs and generate a respective analog output. The summing unit sums the respective analog outputs of the conversion units for generating an analog output. The present invention implements the dynamic element matching technique by randomly rotating the binary-weighted inputs, so as to reduce the manufacturing cost of the digital-to-analog converter.

FIELD OF THE INVENTION

The present invention relates to a signal converter, and moreparticularly to a digital-to-analog converter (DAC) and a performingmethod thereof.

BACKGROUND OF THE INVENTION

Nowadays, DACs are required for converting digital signals to analogsignals in various electronic products, such as communication systems.Current calibration and dynamic element matching (DEM) are the mostcommonly used for low-cost design. In the Institute of Electrical andElectronics Engineers (IEEE) published papers, the cost of the DEMtechnique is lower than that of the current calibration technique.Furthermore, the DEM technique may be applied for various technologiesbecause the DEM encoder is implemented with digital circuits. Thecurrent calibration technique is limited for certain technologiesbecause some of its building blocks are implemented with analogcircuits.

In the DEM technique, inputs are rotated for generating specificoutputs. The DEM technique comprises binary-weighted architectures,thermometer-coded architectures and algorithmic controller embeddedarchitectures. The architectures with algorithmic controllers can beused to decrease the switching occurrence. However, the controllerembedded architectures are more complicated which require moreimplementation cost, and can't be operated. in high-speed applications.The conventional binary-weighted architectures have advantages of lowcost, low complexity, and low power consumption. However, when inputsapproach the Nyquist frequency, the switching occurrence is greatlyincreased and which encounters glitch problems and the linearity istherefore affected. Accordingly, the conventional binary-weightedarchitectures are seldom used. Compared with the conventionalbinary-weighted architectures, the thermometer-coded architectures havea lower switching occurrence and can reduce noises. However, thethermometer-coded architectures must comprise additional controlcircuits, and thus the power consumption and the area cost are higherthan those of the conventional binary-weighted architectures. Besides,the operation speed is limited.

Therefore, there is a need to propose a solution having both theadvantages of the binary-weighted architectures and thethermometer-coded architectures without the disadvantages of theirs.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a digital-to-analogconverter and a performing method thereof.

According to an aspect of the present invention, the digital-to-analogconverter comprises a random rotation unit, a plurality of conversionunits, and a summing unit. The random rotation unit receives a pluralityof binary-weighted inputs and generates a plurality of rotated digitaloutputs according to a random rotation number. The conversion unitsrespectively receive one of the rotated digital outputs and generate arespective analog output. The summing unit sums the respective analogoutputs of the conversion units for generating an analog output.

According to another aspect of the present invention, in the performingmethod of the digital-to-analog converter, the digital-to-analogconverter comprises a random rotation unit, a plurality of conversionunits, and a summing unit. The performing method of thedigital-to-analog converter comprises: the random rotation unit receivesa plurality of binary-weighted inputs and generates a plurality ofrotated digital outputs according to a random rotation number; theconversion units respectively receive one of the rotated digital outputsand generate a respective analog output; and the summing unit sums therespective analog outputs of the conversion units to generate an analogoutput.

The digital-to-analog converter and the performing method thereofaccording to the present invention implements the dynamic elementmatching technique by randomly rotating the binary-weighted inputswithout extra controlling circuits or encoding circuits. As a result,the manufacturing cost of the digital-to-analog converter can bereduced.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a digital-to-analog converter according to the presentinvention;

FIG. 2 shows a corresponding relationship between the binary weightedinputs and the conversion units in the prior arts;

FIG. 3 shows a corresponding relationship between the binary weightedinputs and the conversion units according to the DAC of the presentinvention;

FIG. 4 shows an embodiment of the rotator in FIG. 1;

FIG. 5 shows spurious-free dynamic ranges of the DAC having 10% mismatcherror according to the present invention and the conventionalbinary-weighted architecture;

FIG. 6 shows curves of average switching rates of the conventionalbinary-weighted architecture, the conventional thermometer-codedarchitecture, and the random rotation architecture of the presentinvention;

FIG. 7 shows the SFDRs of the random rotation architecture of thepresent invention, the conventional binary-weighted architecture in JSSC2006, and the conventional binary-weighted architecture in CICC 2001;

FIG. 8 shows a flow chart of a performing method of a digital-to-analogconverter according to the present invention; and

FIG. 9 shows detailed steps in step S800 in FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following descriptions for the respective embodiments are specificembodiments capable of being implemented for illustrations of thepresent invention with referring to appended figures.

Please refer to FIG. 1. FIG. 1 shows a digital-to-analog converter (DAC)according to the present invention. The DAC comprises a random rotationunit 10, a plurality of conversion units U₇˜U₁, and a summing unit 20.

The random rotation unit 10 receives a plurality of binary weightedinputs B₂˜B₀ and generates a plurality of rotated digital outputs W₇˜W₁according to a random rotation number. Specifically, the random rotationunit 10 comprises a pseudo-random number generator (PRNG) 100 and arotator 102. The pseudo-random number generator 100 is utilized forgenerating the random rotation number. The rotator 102 shifts androtates the binary weighted inputs B₂˜B₀ according to the randomrotation number for generating the rotated digital outputs W₇˜W₁.

The conversion units U₇˜U₁ respectively receive one of the rotateddigital outputs W₇˜W₁ and generate one of respective analog outputsY₇˜Y₁. Each of the conversion units U₇˜U₁ may be a current source, aunit capacitor or other suitable elements.

The summing unit 20 sums the respective analog outputs Y₇˜Y₁ forgenerating an analog output Y_(out).

The DAC of the present invention implements the dynamic element matchingtechnique by directly receiving the binary weighted inputs B₂˜B₀ andrandomly rotating the binary weighted inputs B₂˜B₀. The DAC of thepresent invention may be regarded as random rotation architecture.Please refer to FIG. 2 and FIG. 3. FIG. 2 shows a correspondingrelationship between the binary weighted inputs B₂˜B₀ and the conversionunits U₇˜U₁ in the prior arts. FIG. 3 shows a corresponding relationshipbetween the binary weighted inputs B₂˜B₀ and the conversion units U₇˜U₁according to the DAC of the present invention. In the prior arts asshown in FIG. 2, the binary weighted input B₂ controls the fourconversion units U₇˜U₄, the binary weighted input B₁ controls the twoconversion units U₃˜U₂, and the binary weighted input B₀ controls theconversion unit U₁, and so on.

Please refer to FIG. 1 and FIG. 3. When the binary weighted inputs B₂˜B₀are “110” (i.e. corresponding to 6 in decimal) and the pseudo-randomnumber generator 100 generates the random rotation number having aright-rotation direction and a rotation (or called shift) of 4-steps.The right-rotation direction and the rotation of 4-steps are representedas R4 in FIG. 3. The rotator 102 shifts and rotates the binary weightedinputs B₂˜B₀ in FIG. 2 for generating the rotated digital outputs W₇˜W₁in FIG. 1. It is noted that FIG. 3 does not show the rotated digitaloutputs W₇˜W₁ in FIG. 1. FIG. 3 shows the corresponding relationshipbetween the binary weighted inputs B₂˜B₀ and the conversion units U₇˜U₁.After performing the right-rotation of 4-steps, the binary weightedinput B₂ controls the conversion units U₇, U₃, U₂, U₁, the binaryweighted input B₁ controls the conversion units U₆, U₅, and the binaryweighted input B₀ controls the conversion unit U₄. The binary weightedinputs B₂˜B₀ in FIG. 2 and the binary weighted inputs B₂˜B₀ in FIG. 3control different conversion units U₇˜U₁. When the binary weighted inputB₂ is “1”, it means that the conversion units U₇, U₃, U₂, U₁ controlledby the binary weighted input B₂ are selected. When the binary weightedinput B₁ is “1”, it means that the conversion units U₆, U₅ controlled bythe binary weighted input B₁ are selected. As a result, the output is asum of all selected conversion units, that is, the analog outputY_(out)=Y₇+Y₆+Y₅+Y₃+Y₂+Y₁.

Then, when the binary weighted inputs B₂˜B₀ are changed from “110” to“011” (i.e. corresponding to 3 in decimal) and the pseudo-random numbergenerator 100 generates the random rotation number having theright-rotation direction and a rotation of 5-steps. The right-rotationof 5-steps is represented as R5 in FIG. 3. After the rotator 102 shiftsand rotates the binary weighted inputs B₂˜B₀ in FIG. 2 by theright-rotation of 5-steps, the binary weighted input B₂ controls theconversion units U₇, U₆, U₂, U₁, the binary weighted input B₁ controlsthe conversion units U₅, U₄, and the binary weighted input B₀ controlsthe conversion unit U₃. When the binary weighted input B₁ is “1”, itmeans that the conversion units U₅, U₄ controlled by the binary weightedinput B₁ are selected. When the binary weighted input B₀ is “1”, itmeans that the conversion unit U₃ controlled by the binary weightedinput B₀ is selected. As a result, the output is a sum of all selectedconversion units, that is, the analog output Y_(out)=Y₅+Y₄+Y₃.

When the binary weighted inputs B₂˜B₀ are changed from “011” to “111”(i.e. corresponding to 7 in decimal) and the pseudo-random numbergenerator 100 generates the random rotation number having theright-rotation of 1-step. The right-rotation of 1-step is represented asR1 in FIG. 3. After the rotator 102 shifts and rotates the binaryweighted inputs B₂˜B₀ in FIG. 2 by the right-rotation of 1-step, thebinary weighted input B₂ controls the conversion units U₆, U₅, U₄, U₃,the binary weighted input B₁ controls the conversion units U₂, U₁, andthe binary weighted input B₀ controls the conversion unit U₇. When thebinary weighted input B₂ is “1”, it means that the conversion units U₆,U₅, U₄, U₃ controlled by the binary weighted input B₂ are selected. Whenthe binary weighted input B₁ is “1”, it means that the conversion unitsU₂, U₁ controlled by the binary weighted input B₁ are selected. When thebinary weighted input B₀ is “1”, it means that the conversion unit U₇controlled by the binary weighted input B₀ is selected. As a result, theoutput is a sum of all selected conversion units, that is, the analogoutput Y_(out)=Y₇+Y₆+Y₅+Y₄+Y₃+Y₂+Y₁.

When the binary weighted inputs B₂˜B₀ are changed from “111” to “100”(i.e. corresponding to 4 in decimal) and the pseudo-random numbergenerator 100 generates the random rotation number having theright-rotation of 2-steps. The right-rotation of 2-steps is representedas R2 in FIG. 3. After the rotator 102 shifts and rotates the binaryweighted inputs B₂˜B₀ in FIG. 2 by the right-rotation of 2-steps, thebinary weighted input B₂ controls the conversion units U₅, U₄, U₃, U₂,the binary weighted input B₁ controls the conversion units U₇, U₁, andthe binary weighted input B₀ controls the conversion unit U₆. When thebinary weighted input B₂ is “1”, it means that the conversion units U₅,U₄, U₃, U₂ controlled by the binary weighted input B₂ are selected. Theoutput is a sum of all selected conversion units, that is, the analogoutput Y_(out)=Y₅+Y₄+Y₃+Y₂.

Finally, when the binary weighted inputs B₂˜B₀ are changed from “100” to“101” (i.e. corresponding to 5 in decimal) and the pseudo-random numbergenerator 100 generates the random rotation number having theright-rotation of 0-step. The right-rotation of 0-step is represented asR0 in FIG. 3. Since the rotator 102 does not perform any rotation on thebinary weighted inputs B₂˜B₀ in FIG. 2, the binary weighted input B₂controls the conversion units U₇, U₆, U₅, U₄, the binary weighted inputB₁ controls the conversion units U₃, U₂, and the binary weighted inputB₀ controls the conversion unit U₁. When the binary weighted input B₂ is“1”, it means that the conversion units U₇, U₆, U₅, U₄ controlled by thebinary weighted input B₂ are selected. When the binary weighted input B₀is “1”, it means that the conversion unit U₁ controlled by the binaryweighted input B₀ is selected. The output is a sum of all selectedconversion units, that is, the analog output Y_(out)=Y₇+Y₆+Y₅+Y₄+Y₁.

It is noted that the FIG. 3 shows the examples of the right-rotationdirection. In another embodiment, the rotation direction may be aleft-rotation direction or be determined randomly.

Please refer to FIG. 4. FIG. 4 shows an embodiment of the rotator 102 inFIG. 1. The rotator 102 comprises a plurality of multiplexers MUX. Theprinciples of the multiplexers MUX are known for one skilled in the artof the present invention and thus omitted herein. Furthermore, therotator 102 is not limited to the implementation in FIG. 4, and it maybe other implementations.

Please refer to FIG. 5. FIG. 5 shows spurious-free dynamic ranges (SFDR)of the DAC having 10% mismatch error according to the present inventionand the conventional binary-weighted architecture. The DAC according tothe present invention and the conventional binary-weighted architectureare implemented with 6 bits. It can be seen from the comparison that theSFDR of the DAC according to the present invention is better than theSFDR of the conventional binary-weighted architecture by 23.1 dB (71.1dB−48 dB=23.1 dB).

Please refer to FIG. 6. FIG. 6 shows curves of average switching ratesof the conventional binary-weighted architecture, the conventionalthermometer-coded architecture, and the random rotation architecture ofthe present invention. Y-axis is the average switching rate. Thedefinition of the average switching rate is total switchingnumber/sample. X-axis is a normalized frequency. The definition of thenormalized frequency is input frequency/sample frequency (Fin/Fs).Curves C1, C2, C3 respectively represent the conventionalbinary-weighted architecture, the conventional thermometer-codedarchitecture, and the random rotation architecture of the presentinvention. In the same normalized frequency, the smaller averageswitching rate is better. The smaller average switching rate means thatthe switching occurrence is fewer. The switching number refers to anumber of turn-on and turn-off of the conversion units U₇˜U₄.

In a high frequency band, i.e. in the area A1 (about the Nyquistfrequency), the average switching rate of the curve C2 is smallest. Itmeans that the conventional thermometer-coded architecture has the bestperformance. However, extra controlling circuits or encoding circuitsare required in the conventional thermometer-coded architecture, so thatthe required layout area is largest, and the cost and power consumptionare highest too. Accordingly, the conventional thermometer-codedarchitecture is not suitable in high speed portable applications, suchas communication systems. Compared with the switching occurrence of theconventional thermometer-coded architecture, the switching occurrence ofthe random rotation architecture of the present invention (curve C3) inthe area Al can be decreased by about 20%. As a result, a glitch problemof the conventional binary-weighted architecture due to the largeswitching occurrence in the high frequency band can be solved.

In a low frequency band, i.e. in the area A2, the average switching rateof the curve C2 is smallest. It means that the conventionalthermometer-coded architecture has the best performance. However, thecost is the highest as mentioned above. Although the performance of therandom rotation architecture of the present invention (curve C3) in thearea A2 is worse than the performance of the conventionalthermometer-coded architecture, the switching occurrence is usually notlarge in the low frequency band. Accordingly, the effect to lowfrequency band is limited. In addition, for the purpose of increasingthe performance in the low frequency band, the frequency of generatingthe random rotation number from pseudo-random number generator 100 maybe decreased for decreasing the switching occurrence in the lowfrequency band. Preferredly, the frequency is decreased to ½, ¼, . . . ,and so on. The frequency may be set as required.

In summary, the random rotation architecture of the present invention iscapable of solving the glitch problem in the high frequency band (i.e.in the area A1) in the conventional binary-weighted architecture.Although the performance of the random rotation architecture of thepresent invention is worse than the conventional thermometer-codedarchitecture, the present invention does not required extra controllingcircuits or encoding circuits. As a result, the manufacturing (area)cost of the DAC, including digital controlling circuits, analog currentswitches, and conversion units, can be decreased by more than 80%. Theeffect of performance degradation of the present invention in the lowfrequency band (i.e. the area A2) is limited. The random rotationarchitecture of the present invention is capable of increasing theperformance in the low frequency band by decreasing the frequency ofgenerating the random rotation number from the pseudo-random numbergenerator 100.

Please refer to FIG. 7. FIG. 7 shows the SFDRs of the random rotationarchitecture of the present invention, the conventional binary-weightedarchitecture in Journal of Solid-State Circuits (JSSC) 2006, and theconventional binary-weighted architecture in Custom Integrated CircuitsConference (CICC) 2001. It can be seen that the SFDR of the randomrotation architecture of the present invention is better than the SFDRsof the two other architectures. Besides, the implementation area is thesmallest.

The following TABLE 1 shows comparison of the DAC of the random rotationarchitecture of the present invention, the conventional binary-weightedarchitecture or the conventional thermometer-coded architecture inInternational Solid-State Circuit conference (ISSCC) 2011, Transactionson Circuits and Systems I (TCASI) 2010, JSSC 2009, JSSC2006, and JSSC2001.

TABLE 1 present invention ISSCC 2011 TCASI 2010 JSSC 2009 JSSC 2006 JSSC2001 Resolution 10 12 10 12 10 10 (bit) Technology 0.18 μm 90 nm 0.13 μm65 nm 0.18 μm 0.35 μm Sample rate 500 1250 1600 2900 250 1000 (MS/s)I_(load) (mA) 10 16 10 50 10 20 P_(total) (mW) 24 128 23.6 188 22 110BW_(N) (MHz) 250 500 325 100 125 500 Area (mm²) 0.034 0.825 0.5 0.310.35 0.35 SFDR_(DC) (dB) 74 75 74 74 74 74 SFDR_(Nyquist) 61 66 50 N/A60 61 (dB) FOM1 1.07E+04 1.60E+04 1.23E+04 2.18E+03 5.82E+03 4.65E+03FOM2 8.25E+07 7.50E+07 3.29E+07 N/A 4.02E+07 3.52E+07 FOM3 3.14E+051.94E+04 2.46E+04 7.03E+03 1.66E+04 1.33E+04

In TABLE 1, the area refers to an active area of the DAC. BW_(N) refersto a bandwidth for remaining the SFDR of (6×bit) dB. SFDR_(DC) refers toa best SFDR measured in the Nyquist frequency. SFDR_(Nyquist) refers toa worst SFDR measured in the Nyquist frequency. FOM1˜FOM3 refer tofigures of merit commonly used in IEEE and define as follows:

${{FOM}\; 1} = \frac{2^{N} \times {BW}_{N}}{P_{total}}$${{FOM}\; 2} = \frac{2^{\frac{{SFDR}_{DC} - 1.76}{6.02}} \times 2^{\frac{{SFDR}_{N_{yquat}} - 1.76}{6.02}} \times f_{elk}}{P_{total} - {\frac{1}{2}I_{load}^{2} \times R_{load}}}$${{FOM}\; 3} = \frac{2^{N} \times {BW}_{N}}{P_{total} \times {Area}}$

It is noted that values of the above-mentioned FOM1˜FOM3 are the higherthe better. In comparison with the conventional binary-weightedarchitecture or the conventional thermometer-coded architecture, theFOM2 and FOM3 of the present invention are better and the FOM1 of thepresent invention is not bad. As a result, the present invention canimplement a high speed DAC with a low area cost.

Please refer to FIG. 8. FIG. 8 shows a flow chart of a performing methodof a digital-to-analog converter according to the present invention. Thedigital-to-analog converter comprises a random rotation unit, aplurality of conversion units, and a summing unit. Firstly, in stepS800, the random rotation unit receives a plurality of binary-weightedinputs and generates a plurality of rotated digital outputs according toa random rotation number. Each of the conversion units is a currentsource or a unit capacitor. The random rotation number has a rotationdirection and a rotation step. The rotation direction may be aleft-rotation direction, a right-rotation direction, or be determinedrandomly. The rotation refers to a step of the rotation.

In step S820, the conversion units respectively receive one of therotated digital outputs and generate a respective analog output.

In step S840, the summing unit sums the respective analog outputs of theconversion units to generate an analog output.

In one embodiment, the random rotation unit comprises a pseudo-randomnumber generator and a rotator. Step S800 comprises steps shown in FIG.9. In step S8000, the pseudo-random number generator generates therandom rotation number. In step S8020, the rotator shifts and rotatesthe binary weighted inputs according to the random rotation number forgenerating the rotated digital outputs. Furthermore, the frequency ofgenerating the random rotation number may be decreased for decreasingthe switching occurrence in the low frequency band. Preferredly, thefrequency is decreased to ½, ¼, . . . , and so on. The frequency may beset as required.

The present invention has been described with a preferred embodimentthereof and it is understood that many changes and modifications to thedescribed embodiment can be carried out without departing from the scopeand the spirit of the invention that is intended to be limited only bythe appended claims.

1. A digital-to-analog converter, comprising: a random rotation unit,receiving a plurality of binary-weighted inputs and generating aplurality of rotated digital outputs according to a random rotationnumber; a plurality of conversion units, respectively receiving one ofthe rotated digital outputs and generating a respective analog output;and a summing unit, summing the respective analog outputs of theconversion units for generating an analog output.
 2. Thedigital-to-analog converter of claim 1, wherein the random rotation unitcomprises: a pseudo-random number generator, generating the randomrotation number; and a rotator, shifting and rotating the binaryweighted inputs according to the random rotation number for generatingthe rotated digital outputs.
 3. The digital-to-analog converter of claim2, wherein the frequency of generating the random rotation number frompseudo random number generator is reduced for decreasing a switchingoccurrence of digital-to-analog converter in a low frequency band. 4.The digital-to-analog converter of claim 1, wherein each of theconversion units is a current source or a unit capacitor.
 5. Thedigital-to-analog converter of claim 1, wherein the random rotationnumber has a rotation direction and a rotation step.
 6. Thedigital-to-analog converter of claim 5, wherein the rotation directionis a left-rotation direction, a right-rotation direction, or determinedrandomly.
 7. A performing method of a digital-to-analog converter, thedigital-to-analog converter comprising a random rotation unit, aplurality of conversion units, and a summing unit, the performing methodof the digital-to-analog converter comprising: the random rotation unitreceiving a plurality of binary-weighted inputs and generating aplurality of rotated digital outputs according to a random rotationnumber; the conversion units respectively receiving one of the rotateddigital outputs and generating a respective analog output; and thesumming unit summing the respective analog outputs of the conversionunits to generate an analog output.
 8. The performing method of thedigital-to-analog converter of claim 7, wherein the random rotation unitcomprises a pseudo-random number generator and a rotator, and the stepof receiving the binary-weighted inputs and generating the rotateddigital outputs according to the random rotation number comprises: thepseudo-random number generator generating the random rotation number;and the rotator shifting and rotating the binary weighted inputsaccording to the random rotation number for generating the rotateddigital outputs.
 9. The performing method of the digital-to-analogconverter of claim 8, wherein the frequency of generating the randomrotation number from pseudo random number generator is reduced fordecreasing a switching occurrence of digital-to-analog converter in alow frequency band.
 10. The performing method of the digital-to-analogconverter of claim 7, wherein each of the conversion units is a currentsource or a unit capacitor.
 11. The performing method of thedigital-to-analog converter of claim 7, wherein the random rotationnumber has a rotation direction and a rotation step.
 12. The performingmethod of the digital-to-analog converter of claim 11, wherein therotation direction is a left-rotation direction, a right-rotationdirection, or determined randomly.